The present disclosure relates to a frequency dividing circuit dividing a frequency of an input signal and then outputting a resultant signal, and a phase synchronization circuit provided with such a frequency dividing circuit.
A frequency dividing circuit that generates a clock signal having a frequency lower than a frequency of an input clock signal based on the input clock signal is often mounted on a semiconductor device. Here, a value obtained by dividing the frequency of the input clock signal by the frequency of the generated clock signal is referred to as a dividing ratio. A duty ratio of the clock signal generated in such a way may be often desired to be about 50%.
Some of the frequency dividing circuits are configured so as to change the dividing ratio. For example, in Japanese Unexamined Patent Application Publication No. 2007-74636, a frequency dividing circuit capable of switching the dividing ratio between a predetermined odd value and a predetermined even value is disclosed.